[uClinux-dev] Excluding one of n Cores

Michael Schnell mschnell at lumino.de
Tue Jul 30 06:57:15 EDT 2013


On 07/30/2013 12:22 PM, Paul Chavent wrote:
>
> I'm not an expert. But i give you my ("standard" linux kernel) point 
> of view (don't know if it works with uClinux).
GREAT ! As I have Debian or something similar in mind, this might not 
really be "uCLinux", anyway. :-)
In fact, is "uClinux" still defined as noMMU ? I understand that 
regarding the great success of ARM Cortex A8+ chips noMMU is more and 
more  obsolete an "uClinux" might get a synonym for "small embedded", 
with "small" now going up to "1GHz 1GByte".

>
> See the isolcpu kernel parameter.
I'll take a look.
>
> Something like interrupt balancing ?
Not really.
I am not sure how SMP hardware usually is done. I understand that when a 
hardware interrupt happens, exactly one of the cores gets the interrupt 
and starts the ISR. But which one ? Is the assignment "Interrupting 
hardware -> Core Number"  fix ? Is it programmable at system start ? Is 
it done dynamically e.g. according to the performance done by the 
Kernels (i.e. a rather idle Kernel gets interrupted). Is there hardware 
support for this ?

When doing AMP with such SMP-enable hardware, some interrupts need to be 
fixed assigned to the "special purpose" core to trigger the appropriate 
low latency actions there.

>
> I never tried to enable mmu with uclinux. But on a "standard" linux i 
> use mlock to deal with mmu, caches etc.
>
I see.
(I just don't know where to ask embedded "non uCLinux" questions, so I 
thought here  would be the best place for strictly embedded Linux 
questions, even with MMU involved.)

Thanks a lot !
-Michael



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