*SPAM* [uClinux-dev] uClinux port to Lattice's Mico32

[ADP]

On 10/30/07, Michael Schnell <mschnell at lumino.de> wrote:

> My impression is that it could be viable to create a common "arch" for
> several similar ip-core processors (namely NIOS II, MicroBlaze and
> Micro32), in a way that the sub-archs are different only in some
> preprocessor variables. By this, there would be much more impact to the
> effort to bring these processors into the main µCLinux tree.

Agreed, though I'd just like to avoid ending up with too much nested
preprocessor definitions. After all, Linux kernel has just been
maintained avoiding '#ifdef' and the like as much as possible,
preferring a lot of directory 'n files instead of a big source that
would end filled up with macros. According to my opinion this is not
viable, and soft-cores (despites being quite similar) could have
subtle differences we can have trouble to cope with.

> I suppose the same is true for NIOS.
> How is this handled ? Is multiprocessor possible/planned with your port
> ? I do know that the Altera SDK comes with HDL code for a hardware
> semaphore, so that could be usable with multiple processors. It should
> be quite easy to create a custom instruction from the semaphore HDL
> code, instead of using it as a kind of I/O port, if that seems to be viable.
> While I cant comment on your conclusion, I feel that multiprocessor
> support is really critical with a port for the said processors, as it's
> easily possible to configure an FPGA to contain lots of CPU cores.

The very first effort is to port the kernel and let it work on
uniprocessor. Again, I agree with you that SMP will be very
interesting both technically and practically, especially on soft-cores
like Mico32 that do not waste too much cells.
I think HDL for semaphore is great, and can considerably speed up
synchronization. Taking that thing a little further, we can also
imagine a macro that  will take care of context switching, giving much
more speed to task handling.
However, I'm also on embedded programming since several years, but
quite a newbie in fpga and HDL in general.

Andrew