*SPAM* [uClinux-dev] uClinux port to Lattice's Mico32

[ADP]

>
> Are these oft cores quite alike or are there significant differences
> (e.g. "non-load-store" architecture, instruction word length, register
> count, similarities to "traditional" cores, etc.)
>
> -Michael

Yep, Mico32 is a quite simple soft-core based upon RISC architecture.
For the most part of it it resembles both NiosII and, using a lot of
fantasy, MIPS (it has a lot of registers, compared to ARM). Of course,
it currently lacks MMU support. Here's the main characteristics:

- 32x32bit  registers (pc cannot be changes, unlike ARM)
- configurable data/instruction cache using EBR cell
- barrel shifter
- load/store register architecture
- exception vector separated from debug one. This is quite interesting
indeed, letting you to debug even exception vector without too much
trouble.

Indeed it lacks some features that could led to a faster kernel
implementation (or, at least without all of that hassle!):

- registers are not banked across user/exception vector (unlike ARM),
so you must save&restore (namely) the stack in between
- no all-in-one barrel-shifted/conditionally-verified/do-something instruction
- no support for atomic operation used in semaphore handling
- cache can be only invalidated entirely.

Considering this, I've based my port upon the ARM one, taking some
advice from NiosII and (just in a few cases) MIPS one. In my opinion
ARM has a strong support for multi-processor, multi-platform
configuration and since a soft-core can be potentially used on a wide
variety of appliance, it seems to me that starting from ARM was the
right choice.

Any comments about the way to distribute the patch, since it's still
in a very early stage? Perhaps someone wants to join the journey...

Andrew