[uClinux-dev] mach-atmel (Atmel AT91) interrupt controller

Shaun Jackman sjackman at gmail.com
Fri Oct 14 12:18:06 EDT 2005


2005/10/14, Erwin Authried <eauth at softsys.co.at>:
> Am Fre, den 14.10.2005 schrieb Shaun Jackman um 0:54:
> > Finally, I noticed that atmel_timer_inerrupt never reads the
> > timer/counter status register, TC_SR, which I understood was necessary
> > to clear the "RC Compare Status" bit, TC_CPCS, which generates the
> > timer interrupt.
>
> you are right, that seems to be missing!
>
> I think you'll need something like this in atmel_timer_interrupt:
>
>         volatile struct at91_timers* tt = (struct at91_timers*)
> (AT91_TC_BASE);
>         volatile struct at91_timer_channel* tc =
> &tt->chans[KERNEL_TIMER].ch;
>         unsigned long v = tc->sr;

That's almost exactly the patch I used myself. The trouble I'm having
with the interrupt controller is preventing from testing this patch
properly, though.

> Previously, EOICR was written in get_irq_nr_and_base, I have moved that
> into the interrupt service routine so that this is done AFTER handling
> the interrupt. If it doesn't get written in one of those two ways, you
> are locking out  the interrupts.

The AIC_EOICR is now being written in arch/arm/mach-atmel/irq.c
(at91_end_of_isr), which is called by (at91_unmask_and_eoi), which is
the .unmask member of (irqchip at91_chip), which is passed to
(set_irq_chip), whew! All these levels of indirection is somewhat
unnerving for something as simple as acking an interrupt, but I have
verified that the AIC_EOICR is being written.

I'm stymied as to what else could be preventing the interrupt from
taking place. I hope I find it soon so that I can relax this weekend!

I found Linux 2.6.11.8-hsc0 to be a straight forward build. If you had
the time to compile it and give it a test run, I'd be much obliged!
I'd be very interested in hearing your results.

Cheers,
Shaun



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