[uClinux-dev] Re: mach-atmel (Atmel AT91) interrupt controller

Erwin Authried eauth at softsys.co.at
Fri Oct 14 03:47:31 EDT 2005


On Fri, 2005-10-14 at 02:10, Shaun Jackman wrote:
> I found that mach-atmel does in fact read the
> interrupt-vector-register, IVR. This is done in
> include/asm-arm/arch-atmel/entry-macro.S (get_irqnr_and_base).
> 
> The boot hangs at init/calibrate.c (calibrate_delay) line 45: while
> (ticks == jiffies). At this point the timer/counter interrupt, TC1, is
> unmasked, the interrupt-pending-register says there is a TC1 interrupt
> pending. The interrupt-status register says there is no other
> interrupt currently being serviced, the CPSR says that the global IRQ
> interrupt is unmasked, and yet the core-interrupt-status-register says
> that NIRQ is not asserted. Why do I have a pending TC1 interrupt but
> no NIRQ?
> 
> AIC_IMR: 0x20 TC1
> AIC_IPR: 0x20 TC1
> AIC_ISR: 0
> CPSR: 0x60000053 FIQ MODE_SVC
> AIC_CISR: 0x0
> 
> Thanks,
> Shaun
Hello Shaun,
I have done the AT91 2.4 port, but I haven't yet found the time to look
at 2.6.  The IRQ handling looks a bit different in 2.6, it seems to me
like AIC_EOICR isn't been written, without taking a close look at the
2.6 source, have you verified that?
You should take a close look at at the working 2.4 implementation, and
especially at the changes that I have made in entry-armv.S / rev 1.14:

http://cvs.uclinux.org/cgi-bin/cvsweb.cgi/uClinux-2.4.x/arch/armnommu/kernel/entry-armv.S

Previously, EOICR was written in get_irq_nr_and_base, I have moved that
into the interrupt service routine so that this is done AFTER handling
the interrupt. If it doesn't get written in one of those two ways, you
are locking out  the interrupts.

Regards,
Erwin





More information about the uClinux-dev mailing list