[uClinux-dev] uCLinux 2.4.x switch_to init problem

Greg Ungerer gerg at snapgear.com
Mon Oct 3 00:42:30 EDT 2005


Hi Holger,

H. Holfelder wrote:
> thank you for your answer, I think I have done this all. Maybe I forgot 
> something. Here are my crt0_rom.S and my rom.ld:

I can't see any problems in this.

Regards
Greg



> /*----------------------- rom.ld  ----------------------------*/
> 
> MEMORY {
>     rom    : ORIGIN = 0x020040, LENGTH = 0x1c0000
>     ram    : ORIGIN = 0x70000400, LENGTH = 0x1f0000
> }
> 
> SECTIONS {
> 
>     .text : {
>         _stext = . ;
>             *(.text)
>             *(.text.exit)
>             *(.text.lock)
>             *(.exitcall.exit)
>             *(.rodata)
>             *(.rodata.str1.1)
>         . = ALIGN(0x4) ;
>             *(.kstrtab)
>         . = ALIGN(16);          /* Exception table     */
>         __start___ex_table = .;
>             *(__ex_table)
>         __stop___ex_table = .;
> 
>         __start___ksymtab = .;  /* Kernel symbol table  */
>             *(__ksymtab)
>         __stop___ksymtab = .;
>         . = ALIGN(4) ;
>         _etext = . ;
>         __data_rom_start = . ;
>     } > rom
> 
>     .data : AT (ADDR(.text) + SIZEOF(.text)){
>         _sdata = . ;
>         __data_start = . ;
>             *(.data)
>             *(.data.exit)
>         . = ALIGN(0x2000) ;
>             *(.data.init_task)
>         . = ALIGN(0x2000) ;
>         _edata_without_init = . ;
>     } > ram
> 
>     
>     .init BLOCK(4096) : AT (ADDR(.text) + SIZEOF(.text)+ SIZEOF(.data)){
>         __init_begin = .;
>             *(.text.init)
>             *(.data.init)
>         . = ALIGN(16);
>         __setup_start = .;
>             *(.setup.init)
>         __setup_end = .;
>         __initcall_start = .;
>             *(.initcall.init)
>         . = ALIGN(4) ;
>         __initcall_end = .;
>         __init_end = .;
>         _edata = .;
>     } > ram
> 
> 
>     .bss : AT (ADDR(.text) + SIZEOF(.text) + SIZEOF(.init)+ SIZEOF(.data)){
>         _sbss = ALIGN(0x4) ;
>             *(.bss)
>         . = ALIGN(0x4) ;
>             *(COMMON)
>         _ebss = ALIGN(0x4) ;
>         _end = ALIGN(0x4) ;
>     } > ram
> }
> 
> 
> /*****************************************************************************/ 
> 
> 
> /*
>  *  crt0_ram.S -- startup code for MCF5272 ColdFire based MOTOROLA boards.
>  *
>  *  (C) Copyright 2000, Lineo (www.lineo.com).
>  *  (C) Copyright 1999, Greg Ungerer (gerg at lineo.com).
>  *
>  *  1999/02/24 Modified for the 5307 processor David W. Miller
>  *  2005/08/03 Modified for Motorola MCF5206e,
>  *                          changed to crt0_rom.S
>  */
> 
> /*****************************************************************************/ 
> 
> 
> #include "linux/autoconf.h"
> #include "asm/coldfire.h"
> #include "asm/mcfsim.h"
> 
> /*******************************************************/
> /*           Define Chipselects for MFC-Board          */
> /*******************************************************/
> 
> /* ------------------- Defines ----------------------- */
> #define  CS0_ADDR  0x00000000  /* CS0 ... FLASH */
> #define  CS0_MASK  0x001f0000
> #define  CS0_CTRL  0x00000DD3
> #define  CS3_ADDR  0x00007000  /* CS3 ... RAM 1 MB */
> #define  CS3_MASK  0x000F0000
> #define  CS3_CTRL  0x000009C3
> #define  CS5_ADDR  0x00007010  /* CS5 ... RAM-Extension 1MB */
> #define  CS5_MASK  0x000F0000
> #define  CS5_CTRL  0x000009C3
> 
> 
> /*****************************************************************************/ 
> 
> 
> /*
>  *  Motorola M5272C3 ColdFire eval board, chip select and memory setup.
>  *  Changed for Motorola MCF5206e
>  */
> 
> #define MEM_BASE  0x70000400  /* Memory base at address 0 */
> #define MEM_SIZE  0x001F0000  /* Memory size 1Mb */
> #define VBR_BASE  0x70000000  /* Vector address */
> 
> #define MEM_MAX   MEM_BASE+MEM_SIZE      /* Memory end address */
> 
> /*****************************************************************************/ 
> 
> 
> .global _start
> .global _rambase
> .global _ramvec
> .global _ramstart
> .global _ramend
> 
> /*****************************************************************************/ 
> 
> 
> .data
> 
> /*
>  *  Set up the usable of RAM stuff. Size of RAM is determined then
>  *  an initial stack set up at the end.
>  */
> _rambase:
> .long 0
> _ramvec:
> .long 0
> _ramstart:
> .long 0
> _ramend:
> .long 0
> 
> /*****************************************************************************/ 
> 
> 
> .text
> 
> /*
>  *  This is the codes first entry point. This is where it all
>  *  begins...
>  */
> 
> _start:
>   nop         /* Filler */
>   move.w  #0x2700, %sr      /* No interrupts */
> 
> 
> 
> /*****************************************************************/
> /*                 Activate Chipselects for MFC-Board            */
> /*****************************************************************/
> 
>     /* CS0 ... FLASH .................................. */
>   move.w  #CS0_ADDR, %d0      /* CS0 address */
>   move.w  %d0, MCFSIM_CSAR0+MCF_MBAR    /* CS0 address */
>   move.l  #CS0_MASK, %d0      /* CS0 mask */
>   move.l  %d0, MCFSIM_CSMR0+MCF_MBAR    /* CS0 mask */
>   move.w  #CS0_CTRL, %d0      /* CS0 control */
>   move.w  %d0, MCFSIM_CSCR0+MCF_MBAR    /* CS0 control */
> 
>     /* CS3 ...  RAM 1 MB .........................*/
>   move.w  #CS3_ADDR, %d0      /* CS3 address */
>   move.w  %d0, MCFSIM_CSAR3+MCF_MBAR    /* CS3 address */
>   move.l  #CS3_MASK, %d0      /* CS3 mask */
>   move.l  %d0, MCFSIM_CSMR3+MCF_MBAR    /* CS3 mask */
>   move.w  #CS3_CTRL, %d0      /* CS3 control */
>   move.w  %d0, MCFSIM_CSCR3+MCF_MBAR    /* CS3 control */
> 
>     /* CS5 ... RAM-Extension 1MB ..................*/
>   move.w  #CS5_ADDR, %d0      /* CS5 address */
>   move.w  %d0, MCFSIM_CSAR5+MCF_MBAR    /* CS5 address */
>   move.l  #CS5_MASK, %d0      /* CS5 mask */
>   move.l  %d0, MCFSIM_CSMR5+MCF_MBAR    /* CS5 mask */
>   move.w  #CS5_CTRL, %d0      /* CS5 control */
>   move.w  %d0, MCFSIM_CSCR5+MCF_MBAR    /* CS5 control */
> 
> 
>   /*
>    * Setup VBR here, otherwise buserror remap will not work.
>    * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
>    *
>    * bkr at cut.de 19990306
>    *
>    * Note: this is because dBUG points VBR to ROM, making vectors read
>    * only, so the bus trap can't be changed. (RS)
>    */
>   move.l  #VBR_BASE, %a7      /* Note VBR can't be read */
>   movec   %a7, %VBR
> 
> #if 1
>   /*
>    *  Enable CPU internal cache.
>    */
>   move.l  #0x01000000, %d0    /* Invalidate cache cmd */
>   movec %d0, %CACR      /* Invalidate cache */
>   move.l  #0x80000100, %d0    /* Setup cache mask */
>   movec %d0, %CACR      /* Enable cache */
> #endif
> 
>   /*
>    *      Copy data segment from ROM to RAM
>    */
>   lea __data_rom_start, %a0
>   lea _sdata, %a1
>   lea _edata, %a2
> _copy_data:
>   move.l  (%a0)+, %d0                     /* Get next word */
>   move.l  %d0, (%a1)+                     /* Copy to RAM */
>   cmp.l   %a1, %a2                        /* Check if at end */
>   bne     _copy_data
> 
>   /*
>    *  Zero out the bss region.
>    */
>   lea.l _sbss, %a0      /* Get start of bss */
>   lea.l _ebss, %a1      /* Get end of bss */
>   clr.l %d0       /* Set value */
> _clear_bss:
>   move.l  %d0, (%a0)+     /* Clear each word */
>   cmp.l %a0, %a1      /* Check if at end */
>   bne _clear_bss
> 
>         movel   #MEM_BASE, %d0
>         movel   %d0, _rambase
> 
>         movel   #_ebss, %d0
>         movel   %d0, _ramstart
> 
>         movel   #MEM_MAX, %d0
>         movel   %d0, _ramend
> 
>         movel   #VBR_BASE, %d0
>         movel   %d0, _ramvec
> 
>   /*
>    * load the current task pointer and stack
>    */
>   lea   init_task_union, %a0
>   movel   %a0, _current_task
>   lea   0x2000(%a0), %sp
> 
>   /*
>    *  Assember start up done, start code proper.
>    */
>   jsr start_kernel      /* Start Linux kernel */
> 
> _exit:
>   jmp _exit       /* Should never get here */
> 
> /* ----------------------- end crt0_rom.S -------------------*/
> 
> I have defined CAT_ROMARRAY, and the Adress of the file-system showed in 
> bootlog is ok. (I have checked this.)
> Here are some additional Information about the filesystem configuration 
> I have made.
> 
> CONFIG_BLK_DEV_RAM=y
> CONFIG_BLK_DEV_RAM_SIZE=4096
> # CONFIG_BLK_DEV_INITRD is not set
> # CONFIG_BLK_DEV_RAMDISK_DATA is not set
> CONFIG_BLK_DEV_BLKMEM=y
> CONFIG_NOFLASH=y
> 
> #
> # File systems
> #
> CONFIG_AUTOFS4_FS=y     /* Don't know why this is set? */
> CONFIG_RAMFS=y
> CONFIG_PROC_FS=y
> CONFIG_ROMFS_FS=y
> CONFIG_EXT2_FS=y
> 
> Hope you find anything wrong.
> 
> Regards,
> Holger
> 
> _______________________________________________
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> uClinux-dev at uclinux.org
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> This message was resent by uclinux-dev at uclinux.org
> 

-- 
------------------------------------------------------------------------
Greg Ungerer  --  Chief Software Dude       EMAIL:     gerg at snapgear.com
SnapGear -- a CyberGuard Company            PHONE:       +61 7 3435 2888
825 Stanley St,                             FAX:         +61 7 3891 3630
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