[uClinux-dev] Xilnx CPLD problems
hamilton at SEDSystems.ca
Fri Mar 7 15:29:01 EST 2003
I am using Xilinx webpack tools to compile verilog CPLD code for a CPLD on
a new board we are building. Unfortunately the tools are recognizing that
I am using flip-flops in the design but optimizing them away. The
behaviour model works correctly but the post synthesis model does not
work. If anybody has any suggestion, they would be much appreciated.
I know that this is not the best forum but I thought I would send out a
request for help here because I am sure there are people on this list that
know about this.
Kendrick Hamilton E.I.T.
SED Systems, a division of Calian Ltd.
18 Innovation Blvd.
PO Box 1464
Hamilton at sedsystems.ca
Tel: (306) 933-1453
Fax: (306) 933-1486
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