[uClinux-dev] Caches and DMA
davidm at snapgear.com
Fri Apr 19 00:16:37 EDT 2002
Jivin Fabrice Gautier lays it down ...
> Can someone tell me if the kernel expect DMA memory to be not cacheable? ie:
> does the kernel sync the caches after a DMA transfert or does it expect this
> memory not be cacheable/cached in the first place ?
I think it depends on your PCI implementation (HW). I was working on a
SuperH a while back and I needed to flush/invalidate the areas I was using
for DMA to get sane behaviour. It was hooked in somewhere quite cleanly, I
can dig it up if you like,
David McCullough: Ph: +61 7 3435 2815 http://www.SnapGear.com
davidm at snapgear.com Fx: +61 7 3891 3630 825 Stanley St., W'gabba QLD 4102, Oz
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