[uClinux-dev] ARM 946 I-cache problems

fabien.klein at mindspeed.com fabien.klein at mindspeed.com
Wed Nov 28 11:13:48 EST 2001


It is true that the functions used in proc-arm940t have been heavilly 
copied from the arm920 one , but cache handling works OK if the memory 
regions are correcly set at boot time 
You can take a look at this dummy code as an example 
  

    LDR     R0,=0x0000003F     @ ; Cacheable 0x00000000 ~ 0xFFFFFFFF (4 
GB)
    MCR     p15,0,R0,c6,c0,1   @ ; Inst Region 0 (C0)

    LDR     R0,=0x0000003F     @ ; Non-Cacheable 0x00000000 ~ 0xFFFFFFFF 
    MCR     p15,0,R0,c6,c0,0   @ ; Data Region 0 (C0)

    LDR     R0,=0x00800019     @ ; Cacheable Data Region 0x001F0000 ~ 
0x001F1FFF  (8 KB vector/stack use)
    MCR     p15,0,R0,c6,c1,0   @ ; Data Region 1 (C1) higher priority can 
overwrite Region 0

    MOV     R0,#0x01           @ ; (C0 means nothing here)
    MCR     p15,0,R0,c2,c0,1   @ ; enable Inst Region 0 , disable Region 
1~7

    MOV     R0,#0x02
    MCR     p15,0,R0,c2,c0,0   @ ; enable Data Region 1 , disable Region 
0,2~7
    MCR     p15,0,R0,c3,c0  @  ; enable write buffer for Data Region 1 , 
disable the rests

    MOV     R0,#0x3
    MCR     p15,0,R0,c5,c0,1   @ ; enable full access on Inst Region 0 
only
    MOV     R0,#0xF
    MCR     p15,0,R0,c5,c0,0   @ ; enable full access on Data Region 0 and 
1 only

    MRC     p15, 0, R0, c1, c0, 0
    ORR     R0, R0, #0x1
    MCR     p15, 0, R0, c1, c0, 0  @ ; Enable Protection Unit
 
    MRC     p15, 0, R0, c1, c0, 0
    ORR     R0, R0, #0x1000
    MCR     p15, 0, R0, c1, c0, 0  @ ; Enable Inst Cache

    MRC     p15, 0, R0, c1, c0, 0
    ORR     R0, R0, #0x4
    MCR     p15, 0, R0, c1, c0, 0  @ ; Enable Data Cache


there is also an application note from Arm concerning protection unit 
prog, but I can't remember the reference
f.
        






"Thuys, Michiel" <michiel.thuys at intersil.com>
Sent by: owner-uclinux-dev at uclinux.org
11/28/01 03:57 PM
Please respond to uclinux-dev

 
        To:     <uclinux-dev at uclinux.org>
        cc: 
        Subject:        RE: [uClinux-dev] ARM 946 I-cache problems


Hi Durgesh,

A lot of the functions in proc-arm940.S seem to be copied from
proc-arm920.S, which is quite a different processor (having a MMU).
Therefore, you should be careful using those functions as a basis for
the 946. On the platform we use, we have disabled all these functions
because we have a slightly different architecture, so I can't help you
with any details.

Michiel

-----Original Message-----
From: Durgesh Pattamatta [mailto:DPattamatta at valencesemi.com]
Sent: woensdag 28 november 2001 0:41
To: 'uclinux-dev at uclinux.org'; 'uClinux-dev at geekcreek.net'
Subject: [uClinux-dev] ARM 946 I-cache problems


Hi,

I am porting uclinux 2.4.10-uc1 to ARM 946ES processor on ARM Integrator
development platform. I am able to run kernel with busybox 0.52 on this
board without enabling I-cache and D-cache. The kernel works fine with
only
D-cache enabled also. But when I enable I-cache the kernel crashes
randomly
with data aborts or prefetch aborts (mostly after starting kswapd deamon
or
after mounting romfs). I have written cache flush routines (according to
ARM
946 mannual specs) for 946 in proc-arm946.s and linked with kernel. I
have
used the same technique used by proc-arm940.s to hook the flush routines
with kernel. It looks to me that I need to do something more to get
uclinux
kernel working with I-cache enabled. Did anyone face similar kind of
problem
with ARM940T based boards ? Since cache architecture of ARM940 and
ARM946
are similar. 

I would greatly appreciate if somebody could give some pointers/ tips to
solve this I-cache problems.

with best regards,
durgesh
This message resent by the uclinux-dev at uclinux.org list server
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This message resent by the uclinux-dev at uclinux.org list server http://www.uClinux.org/


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