[uClinux-dev] ARM 946 I-cache problems

fabien.klein at mindspeed.com fabien.klein at mindspeed.com
Wed Nov 28 04:12:22 EST 2001


is it a 2.4.10 specific problem?
What about your memory region setup? (I/D cache, Write buffer..set with 
the CP15 register during init )

f. 




Durgesh Pattamatta <DPattamatta at valencesemi.com>
Sent by: owner-uclinux-dev at uclinux.org
11/28/01 12:40 AM
Please respond to uclinux-dev

 
        To:     "'uclinux-dev at uclinux.org'" <uclinux-dev at uclinux.org>, 
"'uClinux-dev at geekcreek.net'" <uClinux-dev at geekcreek.net>
        cc: 
        Subject:        [uClinux-dev] ARM 946 I-cache problems


Hi,

I am porting uclinux 2.4.10-uc1 to ARM 946ES processor on ARM Integrator
development platform. I am able to run kernel with busybox 0.52 on this
board without enabling I-cache and D-cache. The kernel works fine with 
only
D-cache enabled also. But when I enable I-cache the kernel crashes 
randomly
with data aborts or prefetch aborts (mostly after starting kswapd deamon 
or
after mounting romfs). I have written cache flush routines (according to 
ARM
946 mannual specs) for 946 in proc-arm946.s and linked with kernel. I have
used the same technique used by proc-arm940.s to hook the flush routines
with kernel. It looks to me that I need to do something more to get 
uclinux
kernel working with I-cache enabled. Did anyone face similar kind of 
problem
with ARM940T based boards ? Since cache architecture of ARM940 and ARM946
are similar. 

I would greatly appreciate if somebody could give some pointers/ tips to
solve this I-cache problems.

with best regards,
durgesh
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