[uClinux-dev] 2.4.x questions
bkuhn at lineo.com
Thu Nov 15 18:57:43 EST 2001
Travis Griggs schrieb:
> I am told that the SDRAM on the C3 board is not 0 wait state
Theoreticaly, there are no wait states during burst accesses,
but taking Refresh and CAS-Latency into account, you
may have an average of two clock cycles per read or write.
> It would seem like a good idea
> to park the on chip ram right behind the SDRAM,
> and then let the stack grow down from their.
You could archive that by simply modifying the
kernel linker script, but the kernel stack is
usualy 8 KByte in size and the onchip SRAM is
only 4 KByte ... maybe not enough.
Bernhard Kuhn, Software Engineer, Lineo Inc. (Where Open Meets Smart)
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